DK-DEV-5SGXEA7N【PDF 287/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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11-2

Dynamic Power Equation

SV51013

2013.05.06

Dynamic Power Equation

Figure 11-1: Dynamic Power

The following equation shows how to calculate dynamic power where P is power, C is the load capacitance,

and V is the supply voltage level.

The equation shows that power is design-dependent and is determined by the operating frequency of your

design. Stratix V devices minimize static and dynamic power using advanced process optimizations. This

technology allows Stratix V designs to meet specific performance requirements with the lowest possible

power.

Programmable Power Technology

Stratix V devices offer the ability to configure portions of the core, called tiles, for high-speed or low-power

mode of operation performed by the Quartus II software without user intervention. Setting a tile to high-

speed or low-power mode is accomplished with on-chip circuitry and does not require extra power supplies

brought into the Stratix V device. In a design compilation, the Quartus II software determines whether a

tile should be in high-speed or low-power mode based on the timing constraints of the design.

Stratix V tiles consist of the following:

? Memory logic array block (MLAB)/ logic array block (LAB) pairs with routing to the pair

? MLAB/LAB pairs with routing to the pair and to adjacent digital signal processing (DSP)/ memory block

routing

? TriMatrix memory blocks

? DSP blocks

? PCI Express ? (PCIe ? ) hard IP

? Physical coding sublayer (PCS)

All blocks and routing associated with the tile share the same setting of either high-speed or low-power

mode. By default, tiles that include DSP blocks or memory blocks are set to high-speed mode for optimum

performance. Unused DSP blocks and memory blocks are set to low-power mode to minimize static power.

Clock networks do not support programmable power technology.

With programmable power technology, faster speed grade FPGAs may require less power because there are

fewer high-speed MLAB and LAB pairs, when compared with slower speed grade FPGAs. The slower speed

grade device may have to use more high-speed MLAB and LAB pairs to meet performance requirements.

The Quartus II software sets unused device resources in the design to low-power mode to reduce the static

power. It also sets the following resources to low-power mode when they are not used in the design:

? LABs and MLABs

? TriMatrix memory blocks

? DSP blocks

If a phase-locked loop (PLL) is instantiated in the design, you may assert the areset pin high to keep the

PLL in low-power mode.

Altera Corporation

Power Management in Stratix V Devices

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